1. Field of the Invention
The present invention relates to a driving method of a plasma display panel (PDP), and a plasma display device. More specifically, the present invention relates to an energy recovery circuit of the PDP.
2. Background Description
A PDP is a flat panel display that uses plasma generated by gas discharge to display characters or images. It includes, depending on its size, more than several scores to millions of pixels arranged in a matrix pattern. Such a PDP is classified as a direct current (DC) type or an alternating current (AC) type according to its discharge cell structure and the waveform of the driving voltage applied thereto.
The DC PDP has electrodes exposed to a discharge space to allow DC to flow through the discharge space while the voltage is applied, and thus requires a resistance for limiting the current. To the contrary, the AC PDP has electrodes covered with a dielectric layer that forms a capacitor to limit the current and protect the electrodes from the impact of ions during discharge. Thus, the AC PDP generally has a longer lifetime than the DC PDP.
FIG. 1 is a partial perspective view of an AC PDP.
Pairs of scan electrodes 4 and sustain electrodes 5 are arranged in parallel on a first glass substrate 1 and are covered with a dielectric layer 2 and a protective layer 3. On a second glass substrate 6, a plurality of address electrodes 8 covered with an insulating layer 7 are arranged. Barrier ribs 9 are formed in parallel with the address electrodes 8 on the insulating layer 7, which is interposed between the address electrodes 8. A fluorescent material 10 is formed on the surface of the insulating layer 7 and on both sides of the barrier ribs 9. The first and second glass substrates 1 and 6 are arranged face-to-face with a discharge space 11 formed therebetween, and the scan electrodes 4 and the sustain electrodes 5 lie normal to the address electrodes 8. The discharge space at the intersection between the address electrode 8 and the pair of scan electrode 4 and sustain electrode 5 forms a discharge cell 12.
FIG. 2 shows an arrangement of electrodes in the PDP.
The PDP has a pixel matrix consisting of mxn discharge cells (or pixels). In the PDP, address electrodes A1 to Am are arranged in columns, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn are alternately arranged in rows. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 in FIG. 1.
In general, a single frame is divided into a plurality of subfields, and the subfields are driven in the AC PDP. Each subfield includes a reset period, an address period, and a sustain period with respect to temporal operation variations.
The reset period is for initiating the status of each cell to facilitate the addressing operation. The addressing period is for selectively turning cells on and off and applying an address voltage to the turned on cells (i.e., addressed cells) to accumulate wall charges. The sustain period is for applying sustain pulses and causing a sustain-discharge for displaying an image on the addressed cells.
The discharge spaces between the scan and sustain electrodes and between the address electrode side and the scan/sustain electrode side act as a capacitance load (hereinafter, referred to as “panel capacitor”), so capacitance exists on the panel. Due to the capacitance of the panel capacitor, a reactive power is needed so as to apply a waveform for the sustain-discharge. Thus the PDP driver circuit includes a power recovery circuit for recovering the reactive power and reusing it.
An example of such a power recovery circuit is described in U.S. Pat. Nos. 4,866,349 and 5,081,400 issued to L. F. Weber.
This circuit repeatedly transfers energy of the panel to a power recovery capacitor or transfers energy stored in the power recovery capacitor to the panel using a resonance between the panel capacitor and the inductor, thus recovering the effective power. In this circuit, however, the rising/falling time of the panel voltage is dependent upon the time constant LC determined by the inductance L of the inductor and the capacitance C of the panel capacitor. The rising time of the panel voltage is equal to the falling time because the time constant LC is constant. For a faster rising time of the panel voltage, the switch coupled to the power source has to be hard-switched during the rise of the panel voltage, in which case stress on the switch increases. The hard-switching operation also causes a power loss and increases the effect of electromagnetic interference (EMI).